NVIDIA GPUs face a latency gap in ultra-high-interactivity inference despite high throughput capabilities, as users increasingly pay premium prices for faster tokens and lower latency. Frontier AI labs like OpenAI are evaluating purpose-built systems, including Cerebras and NVIDIA Groq LPUs, for interactive workloads such as real-time assistants and full-duplex voice, where response delay is immediately perceptible. An 8-GPU HGX B200 server offers a theoretical HBM memory bandwidth of 64 TB/s in aggregate, suggesting up to 3,047 tokens/s/user at batch size 1 for GLM-5 at NVFP4, but GPUs fall short due to kernel launch and synchronization overhead, which dominates as token latency approaches sub-millisecond Time Per Output Token ranges. Memory bandwidth increases 2–3× per generation, but memory latency has not improved. TileRT addresses this by statically compiling the entire decode graph into a single persistent kernel on NVIDIA GPUs, maximizing overlap across computation, memory, and communication. On the InferenceX GLM5 FP8 744B benchmark on a single B200 decode server, TileRT reaches up to 500 tokens/s/user, approximately 3× faster than GB300 NVL72 with traditional engines, and achieves up to 2x faster interactivity iso-cost per output token. With PD disaggregation, TileRT handles latency-sensitive decode while vLLM and SGLang serve prefill. TileRT is deployed in production at Xiaomi