IBM has unveiled a 0.7 nm (7 angstroms) process node technology using a Nanostack architecture, enabling 100 billion transistors on a chip the size of a human fingernail—twice as many as its 2nm chip from 2021. The company estimates a 50% performance increase or a 70% improvement in energy efficiency over predecessors, though the 0.7 nm figure is a marketing term, as the distance between transistors remains around 40 nm. The breakthrough involves a 3D architecture stacking transistors made of three nanosheets 5 nm thick, separated by a 9 nm gap. At the VLSI 2026 conference, IBM reported a 40% improvement in SRAM cell scaling, critical for AI accelerators where memory is often the bottleneck. IBM transfers the technology to partners Samsung and Japan's Rapidus, with first commercial products expected within five years and relevance for at least a decade.