Cadence and Samsung Foundry announced a multi-year expansion of their collaboration to develop a full portfolio of Memory and Interface IP certified for Samsung Foundry’s second-generation 2nm process technology. The signoff-ready platform integrates Cadence’s agentic AI digital, custom, 3D-IC, and system design and analysis flows to accelerate advanced silicon implementation for high-performance data centers, edge computing, and intelligent consumer devices. The certified EDA architecture combines the Innovus Implementation System, Virtuoso Studio, and the Integrity 3D-IC Platform, while the verification framework relies on the Voltus IC Power Integrity solution, Quantus extraction, Tempus timing analysis, and the Pegasus Verification System. The place-and-route optimization pipeline deploys the Genus Synthesis Solution and Cadence Cerebrus Intelligent Chip Explorer. The platform establishes a planning flow for hybrid copper bonding technology inside Samsung’s 3D Cube-H architecture. The interface IP portfolio covers serial de-serializer lanes, PCIe, and UCIe connections, alongside custom integration of NVIDIA NVLink-C2C interconnect systems and CUDA-X GPU-accelerated simulation libraries. The hardware node has achieved active deployment through edge-computing developer Ambarella, which utilizes the certified PCIe 5.0 IP and system design kits to construct its next-generation 2nm edge AI SoC platform for autonomous machines, robotics, and multi-sensor edge perception applications.