TSMC is building a multi-stage packaging roadmap where different forms of glass solve different engineering problems at different times, rather than making a single transition from silicon and organic materials to glass. The first step is panelization through CoPoS, or Chip-on-Panel-on-Substrate, which moves advanced packaging from a circular wafer format toward a rectangular panel architecture, with glass initially serving primarily as a temporary carrier for large-area redistribution-layer processing. At a later stage, glass may move deeper into the package as a structural substrate, and only after the manufacturing ecosystem matures could glass become a practical interposer platform for the largest AI systems. CoPoS addresses the limits of wafer-based manufacturing, glass core substrates address the mechanical and dimensional limits of organic substrates, and glass interposers address the electrical and routing limits of existing interposer architectures. TSMC’s CoWoS platform, which uses a wafer-based process to integrate GPUs, ASICs and HBM through silicon interposers or redistribution-layer structures, is constrained by the geometry of a circular wafer as AI packages become larger.