Amid a global memory shortage, leading AI accelerator makers are adopting a “despec” strategy, lowering memory specifications for next-generation products to prioritize shipment volumes over peak performance. According to industry sources on August 8, Nvidia revised down the high-bandwidth memory (HBM) specification for its next-generation AI accelerator “Rubin Ultra” from the initially planned 16-stack HBM4E to 12 stacks, and is considering options such as an 8-stack HBM4E or adopting 8- or 12-stack HBM4 as in the previous model. AMD is also reportedly likely to release its next-generation accelerator MI400 in both 8-stack and 12-stack HBM4 versions. The shift follows supply shortages across the global memory semiconductor market, including the most advanced HBM segment, creating a bottleneck that blocks product shipments. Market research firm TrendForce explained that DRAM shortages expected next year severely limit wafer capacity for HBM production, while verification schedules for 12-stack HBM4E and yield ramp-up uncertainty have prompted key AI chip players to lower memory specifications. Nvidia faces a trade-off: if 12-stack HBM4E verification and mass production succeed, the Rubin Ultra’s input/output (I/O) speed could reach 14–16Gbps, surpassing the previous generation’s 8–11.7Gbps; if it optimizes for HBM4 instead, I/O speed will remain