IBM unveiled the world's first sub-1-nanometer chip technology, a transistor architecture at the 0.7nm (7-angstrom) node, on June 25 from its Yorktown Heights, New York headquarters. The breakthrough involves building transistors in three dimensions rather than two, using a new architecture called "nanostack" that stacks and staggers transistors through 3D sequential integration. The new chip packs nearly 100 billion transistors onto a piece of silicon the size of a fingernail, almost double the density of the 2nm chip IBM unveiled in 2021. IBM says the chip delivers up to 50% more performance or up to 70% greater energy efficiency than its 2nm chips, gains it expects to benefit generative AI, cloud infrastructure, and next-generation devices. IBM projects production in as little as five years. IBM noted that a node name like "0.7nm" or "2nm" is no longer a literal physical measurement but refers to a generation of manufacturing technology. In separate research presented at the VLSI 2026 symposium, IBM showed nanostack delivering about 40% more density in SRAM.