Huawei is finishing its next generation of AI accelerators faster than expected, planning to deliver the Ascend 960DT for training AI models as early as the first quarter of 2027, with the inference-adapted Ascend 960PR expected in the third quarter of 2027. The Ascend 960DT is Huawei’s first publicly known accelerator with High Bandwidth Memory, with 288 GB across eight memory stacks and a total transfer rate of 9.6 TB/s, though it remains unclear where the memory originates from. Huawei claims a maximum computing power of four quadrillion operations per second (4 Petaflops) in FP4, providing no information on integer operations. The Ascend 960PR doubles FP4 computing power at the expense of memory expansion, with 192 GB and a 2.4 TB/s transfer rate, and an initial illustration suggests cheaper LPDDR RAM might be used instead of HBM. An Atlas 960E Superpod can accommodate up to 4096 Ascend-960 accelerators, reaching a maximum computing power of 16 Exaflops and, for DT chips, over a Petabyte of HBM capacity. Huawei relies on optical connections between accelerators and boards, aiming to scale beyond a Superpod toward one million Ascend chips, with new generations expected annually: the Ascend 970 in 2028 with 14 FP4 Petaflops and faster memory, and the Ascend 980