Cadence has certified its AI-driven digital and custom reference flows for Intel Foundry's 18A-P and 14A process technologies, based on the latest Intel Foundry process design kits (PDKs), to provide a signoff-ready path for customers deploying advanced AI, high-performance computing (HPC), and mobile systems-on-chip (SoCs). The collaboration builds on previous agreements, including design intellectual property (IP) optimisation for Intel 18A and 18A-P, and a multi-year Design Technology Co-Optimization (DTCO) agreement targeting Intel 14A. The companies co-optimized tools to leverage innovations such as RibbonFET gate-all-around transistors and advanced backside power delivery technologies like PowerVia and PowerDirect, aiming to help customers achieve power, performance, and area (PPA) gains while reducing design risk and time to market. Cadence is a founding member of the Intel Foundry Accelerator Ecosystem Alliance, which focuses on interoperable, scalable chiplet solutions. Shawn Han, Senior Vice President and General Manager, Foundry Services, Intel Corp., said co-optimized, certified design flows and silicon-validated IP provide greater confidence for designing on next-generation Intel Foundry technologies. The certified flows cover Cadence's AI-driven implementation, verification, and signoff solutions, tuned to the PDKs for Intel 18A-P and Intel 14A. The companies also co-developed an advanced packaging reference design flow supporting Intel Foundry's