Intel is challenging TSMC’s lead in the 2.5D packaging market with its EMIB technology, Intel Foundry packaging director Lee Kyu-oh said at ISMP 2026 on November 4 at the Paradise Hotel in Busan, South Korea. Lee said the interposer process has a wafer utilization rate of around 60%, while the bridge approach exceeds 90%, indicating higher cost efficiency. He highlighted “EMIB-T,” which embeds through-silicon vias inside bridges to secure power delivery paths, and said embedding TSVs in all bridges will become the trend. Industry sources said Google’s TPU v9 lineup will use Intel’s EMIB-T for HumuFish and TriggerFish, while WhaleFish will use TSMC’s CoWoS-L; Amazon is also reportedly planning to adopt EMIB-T for its own AI chips. AI semiconductors commercialized this year integrate up to 12 HBM stacks and more than 20 EMIB bridges in packages measuring up to 120x120mm, while products under development target packages of 120x180mm or larger with at least 16 HBM stacks and more than 38 bridges. Intel projects that packages expanding to 240x240mm with more than 32 HBM stacks will require more than 70 bridges. EMIB silicon bridges are reportedly produced by Taiwan-based foundry UMC using mature 12-inch processes at its Taiwan and Singapore fabs.